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74ABT273CSC

74ABT273CSC Description

74ABT273CSC Description

74ABT273CSC Categories

74ABT273CSC Manufacturer

74ABT273CSC Datasheet (PDF)

74ABT273CSC Datasheet
74ABT273

74ABT273CSC Price & Availability


Check 74ABT273CSC Price & Availability at Canics

74ABT273CSC Features

  • Eight edge-triggered D-type flip-flops
  • Buffered common clock
  • Buffered, asynchronous Master Reset
  • See ABT377 for clock enable version
  • See ABT373 for transparent latch version
  • See ABT374 for 3-STATE version
  • Output sink capability of 64 mA, source capability of 32 mA
  • Guaranteed latchup protection
  • High impedance glitch free bus loading during entire power up and power down cycle
  • Non-destructive hot insertion capability
  • Disable time less than enable time to avoid bus contention

74ABT273CSC Description

    The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) inputs load and reset (clear) all flip-flops simultaneously.

    74ABT273CSC Parameters

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    Keywords
    74ABT273CSC Data Sheet 74ABT273CSC Spec 74ABT273CSC Application Notes 74ABT273CSC Distributor
    74ABT273CSC Circuit 74ABT273CSC Reference 74ABT273CSC PDF 74ABT273CSC RoHS