74ABT273CSC Description74ABT273CSC Description74ABT273CSC Categories74ABT273CSC Manufacturer
74ABT273CSC Datasheet (PDF)
74ABT273CSC Price & Availability
74ABT273CSC Features- Eight edge-triggered D-type flip-flops
- Buffered common clock
- Buffered, asynchronous Master Reset
- See ABT377 for clock enable version
- See ABT373 for transparent latch version
- See ABT374 for 3-STATE version
- Output sink capability of 64 mA, source capability of 32 mA
- Guaranteed latchup protection
- High impedance glitch free bus loading during entire power up and power down cycle
- Non-destructive hot insertion capability
- Disable time less than enable time to avoid bus contention
74ABT273CSC DescriptionThe ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) inputs load and reset (clear) all flip-flops simultaneously. 74ABT273CSC Parameters
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