74ABT377 Description74ABT377 Categories74ABT377 Manufacturer
74ABT377 Datasheet (PDF)
74ABT377 Price & Availability
74ABT377 Features- Clock enable for address and data synchronization applications
- Eight edge-triggered D-type flip-flops
- Buffered common clock
- See ABT273 for master reset version
- See ABT373 for transparent latch version
- See ABT374 for 3-STATE version
- Output sink capability of 64 mA, source capability of 32 mA
- Guaranteed latchup protection
- High impedance glitch free bus loading during entire power up and power down cycle
- Non-destructive hot insertion capability
- Disable time less than enable time to avoid bus contention
74ABT377 DescriptionThe ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE#) is LOW. 74ABT377 Parameters
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