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74ALVC16373MTD

74ALVC16373MTD Description

74ALVC16373MTD Description

74ALVC16373MTD Categories

74ALVC16373MTD Manufacturer

74ALVC16373MTD Datasheet (PDF)

74ALVC16373MTD Datasheet
74ALVC16373

74ALVC16373MTD Price & Availability


Check 74ALVC16373MTD Price & Availability at Canics

74ALVC16373MTD Features

  • 1.1V to 3.6V VCC supply operation
  • 3.6V tolerant inputs and outputs
  • tPD (In to On) 3.5 ns max for 3.0V to 3.6V VCC 3.9 ns max for 2.3V to 2.7V VCC 6.8 ns max for 1.65V to 1.95V VCC
  • Power-off high impedance inputs and outputs
  • Support live insertion and withdrawal (Note 1)
  • Uses patented noise/EMI reduction circuitry
  • Latchup conforms to JEDEC JED78
  • ESD performance: Human body model > 2000V Machine model > 200V
  • Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)

74ALVC16373MTD Description

    The ALVC16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the outputs are in a high impedance state.

    74ALVC16373MTD Parameters

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    Keywords
    74ALVC16373MTD Data Sheet 74ALVC16373MTD Spec 74ALVC16373MTD Application Notes 74ALVC16373MTD Distributor
    74ALVC16373MTD Circuit 74ALVC16373MTD Reference 74ALVC16373MTD PDF 74ALVC16373MTD RoHS