74F676SPC

Fairchild Semiconductor

74F676SPC Datasheet

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The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P₀-P₁₅) inputs is entered on the falling edge of the Clock Pulse (CP#) input signal. When M is LOW, data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position. A HIGH signal on the Chip Select (CS#) input prevents both parallel and serial operations.

74F676, 74F676PC, 74F676SC, 74F676SCX