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74LVT16373MTDX

74LVT16373MTDX Description

74LVT16373MTDX Description

74LVT16373MTDX Categories

74LVT16373MTDX Manufacturer

74LVT16373MTDX Datasheet (PDF)

74LVT16373MTDX Datasheet
74LVT16373, 74LVTH16373

74LVT16373MTDX Price & Availability


Check 74LVT16373MTDX Price & Availability at Canics

74LVT16373MTDX Features

  • Input and output interface capability to systems at 5V VCC
  • Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16373), also available without bushold feature (74LVT16373)
  • Live insertion/extraction permitted
  • Power Up/Power Down high impedance provides glitch-free bus loading
  • Outputs source/sink -32 mA/+64 mA
  • Functionally compatible with the 74 series 16373
  • Latch-up performance exceeds 500 mA
  • ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
  • Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)

74LVT16373MTDX Description

    The LVT16373 and LVTH16373 contain sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the outputs are in a high impedance state.

    74LVT16373MTDX Parameters

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    Keywords
    74LVT16373MTDX Data Sheet 74LVT16373MTDX Spec 74LVT16373MTDX Application Notes 74LVT16373MTDX Distributor
    74LVT16373MTDX Circuit 74LVT16373MTDX Reference 74LVT16373MTDX PDF 74LVT16373MTDX RoHS