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GTLP6C816AMTC Datasheet (PDF)
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GTLP6C816AMTC Features- Interface between LVTTL and GTLP logic levels
- Designed with edge rate control circuitry to reduce output noise on the GTLP port
- VREF pin provides external supply reference voltage for receiver threshold adjustibility
- Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
- TTL compatible driver and control inputs
- Designed using Fairchild advanced BiCMOS technology
- Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
- Power up/down and power off high impedance for live insertion
- Open drain on GTLP to support wired-or connection
- A Port source/sink -24mA/+24mA
- B Port sink +50mA
- 1:6 fanout clock driver for TTL port
- 1:2 fanout clock driver for GTLP port
- Low voltage version of GTLP6C816
GTLP6C816AMTC DescriptionThe GTLP6C816A is a clock driver that provides LVTTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL(P) logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. GTLP6C816AMTC Parameters
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