GTLP6C817MTCX DescriptionGTLP6C817MTCX DescriptionGTLP6C817MTCX CategoriesGTLP6C817MTCX Manufacturer
GTLP6C817MTCX Datasheet (PDF)
GTLP6C817MTCX Price & Availability
GTLP6C817MTCX Features- Interface between LVTTL and GTLP logic levels
- Designed with edge rate control circuitry to reduce output noise on the GTLP port
- VREF pin provides external supply reference voltage for receiver threshold adjustibility
- Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
- TTL compatible driver and control inputs
- Designed using Fairchild advanced CMOS technology
- Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
- Power up/down and power off high impedance for live insertion
- 5V over voltage tolerance on LVTTL ports
- Open drain on GTLP to support wired-or connection
- A Port source/sink -12mA/+12mA
- B Port sink +40mA
- 1:6 fanout clock driver for TTL port
- 1:2 fanout clock driver for GTLP port
GTLP6C817MTCX DescriptionThe GTLP6C817 is a low drive clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the GunningTransceiver logic (GTL) JEDEC standard JESD8-3. GTLP6C817MTCX Parameters
Products Similar to GTLP6C817MTCX
Other Components
58583-2 MAX6426UK42+T ALS31A332NF400 EBC05DREI-S93 3113-1-00-15-00-00-08-0
Keywords
| GTLP6C817MTCX Data Sheet |
GTLP6C817MTCX Spec |
GTLP6C817MTCX Application Notes |
GTLP6C817MTCX Distributor |
| GTLP6C817MTCX Circuit |
GTLP6C817MTCX Reference |
GTLP6C817MTCX PDF |
GTLP6C817MTCX RoHS |
|