HY5DU121622BT-D43

HY5DU121622BT-D43 Manufacturer

HY5DU121622BT-D43 Description

HY5DU121622BT-D43 Categories

HY5DU121622BT-D43 Datasheet (PDF)

HY5DU121622BT-D43 Price & Availability

HY5DU121622BT-D43 Features

• VDD, VDDQ = 2.5V +/- 0.2V
• VDD, VDDQ = 2.6V +/- 0.1V(DDR400)
• All inputs and outputs are compatible with SSTL_2 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
• On chip DLL align DQ and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable /CAS latency 2 / 2.5 / 3 supported
• Programmable burst length 2 / 4 / 8 with both sequential and interleave mode
• Internal four bank operations with single pulsed /RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Full and Half strength driver option controlled by EMRS

HY5DU121622BT-D43 Parameters

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