| ACTS74MS Description | | D-Flip Flop, Dual, with Set and Reset, TTL Inputs, Rad-Hard, Advanced Logic, CMOS | | ACTS74MS Vendor | | Intersil | | ACTS74MS Categories | | | ACTS74MS Features | - Devices QML Qualified in Accordance with MIL-PRFF-38535
- Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96713 and Intersil�s QM Plan
- 1.25 Micron Radiation Hardened SOS CMOS
- Total Dose >300K RAD (Si)
- Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)
- SEU LET Threshold >100 MEV-cm2/mg
- Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
- Dose Rate Survivability >1012 RAD (Si)/s, 20ns Pulse
- Latch-Up Free Under Any Conditions
- Military Temperature Range -55�C to +125�C
- Significant Power Reduction Compared to ALSTTL Logic
- DC Operating Voltage Range 4.5V to 5.5V
- Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
- Input Current ≤ 1�A at VOL, VOH
- Fast Propagation Delay 20ns (Max), 13ns (Typ)
| | ACTS74MS Datasheet and Application Notes | |
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