HI5767 Datasheet

• Sampling Rate 20/40/60MSPS
• 8.8 Bits at fIN = 10MHz, fS = 40MSPS
• Low Power at 40MSPS 310mW
• Wide Full Power Input Bandwidth 250MHz
• On-Chip Sample and Hold
• Internal 2.5V Band-Gap Voltage Reference
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage +5V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs 3.0V/5.0V
• Offset Binary or Two?s Complement Output Format

• Sampling Rate 20/40/60MSPS
• 8.8 Bits at fIN = 10MHz, fS = 40MSPS
• Low Power at 40MSPS 310mW
• Wide Full Power Input Bandwidth 250MHz
• On-Chip Sample and Hold
• Internal 2.5V Band-Gap Voltage Reference
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage +5V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs 3.0V/5.0V
• Offset Binary or Two's Complement Output Format

The HI5767 is a monolithic, 10-bit, analog-to-digital converter fabricated in a CMOS process. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its high sample clock rate is made possible by a fully differential pipelined architecture with both an internal sample and hold and internal band-gap voltage reference.

The 250MHz Full Power Input Bandwidth and superior high frequency performance of the HI5767 converter make it an excellent choice for implementing Digital IF architectures in communications applications. The HI5767 has excellent dynamic performance while consuming only 310mW power at 40MSPS. Data output latches are provided which present valid data to the output bus with a latency of 7 clock cycles. The HI5767 is offered in 20MSPS, 40MSPS and 60MSPS sampling rates.