| DS1004 Description | | 5-Tap High-Speed Silicon Delay Line | | DS1004 Vendor | | Maxim | | DS1004 Categories | | | DS1004 Features | - All-silicon timing delay circuit
- 5 delayed clock phases per input
- Input to Tap 1 delay set at 5ns
- Taps 2-5 delay range: 2, 3, 4, or 5ns
- Nominal delay tolerances of ±1.5ns
- Same accuracy for leading and trailing edges
- Low-power CMOS with TTL compatibility
- Vapor phase, IR, and wave solderable
| | DS1004 Datasheet and Application Notes | | | Parameter | Value | | Number of Taps | 5 | | Delay to First Tap (ns) | 5 | | Tap Increment (ns) | 2,3,4,5 | | Available Total Delays (ns) | 13,17,21,25 | | Supply Voltage | 5V ±5% | | Package | 8/PDIP.300 | | Package | 8/SO.150 | | Price @ 1k | $6.54 |
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