| DS1005 Description | | 5-Tap Silicon Delay Line | | DS1005 Vendor | | Maxim | | DS1005 Categories | | | DS1005 Features | - All-silicon timing delay circuit
- 5 taps, equally spaced
- Delay tolerance +2ns or ±3%, whichever is greater
- Leading and trailing edge accuracy
- Low-power CMOS with TTL compatibility
- Vapor phase, IR, and wave-solderability
| | DS1005 Datasheet and Application Notes | | | Parameter | Value | | Number of Taps | 5 | | Delay to First Tap (ns) | 12 to 50 | | Tap Increment (ns) | 12 to 50 | | Available Total Delays (ns) | 60 to 250 | | Supply Voltage | 5V ±5% | | Package | 14/PDIP.300 | | Package | 16/SOIC.300 | | Package | 8/PDIP.300 | | Price @ 1k | $2.70 |
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