| DS1010 Description | | 10-Tap Silicon Delay Line | | DS1010 Vendor | | Maxim | | DS1010 Categories | | | DS1010 Features | - All-silicon timed delay circuit
- 10 equally spaced taps
- Delay tolerance ±2ns or 5%, whichever is greater
- Stable, precise delays; leading and trailing edge accuracy
- Low-power CMOS with TTL compatibility
- Vapor phase, IR, and wave-solderable
| | DS1010 Datasheet and Application Notes | | | Parameter | Value | | Number of Taps | 10 | | Delay to First Tap (ns) | 5 to 100 | | Tap Increment (ns) | 5 to 100 | | Available Total Delays (ns) | 50 to 1000 | | Supply Voltage | 5V ±5% | | Package | 14/PDIP.300 | | Package | 16/SOIC.300 | | Price @ 1k | $4.10 |
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