DS31256

DS31256 Description

Maxim

256 independent, bidirectional HDLC channels
Up to 132Mbps full-duplex throughput
Supports up to 64 T1 or E1 data streams
16 physical ports (16 Tx and 16 Rx) that can be independently configured for channelized or unchannelized operation
Three fast (52Mbps) ports; other ports capable of speeds up to 10Mbps (unchannelized)
Channelized ports can each handle one, two, or four T1 or E1 lines
Per-channel DS0 loopbacks in both directions
Over-subscription at the port level
Transparent mode supported
On-board bit error-rate tester (BERT) with automatic error insertion capability
BERT function can be assigned to any HDLC channel or any port
Large 16kB FIFO in both receive and transmit directions
Efficient scatter/gather DMA maximizes memory efficiency
Receive data packets are time-stamped
Transmit packet priority setting
V.54 loopback code detector
Local bus allows for PCI bridging or local access
Intel or Motorola bus signals supported
Backward compatibility with DS3134
33MHz 32-bit PCI (V2.1) interface
3.3V low-power CMOS with 5V tolerant I/O
JTAG support IEEE 1149.1
256-pin plastic BGA (27mm x 27mm)
Features continued on page 6 of the PDF data sheet

DS31256 Data Sheet	DS31256 Spec	DS31256 Application Notes	DS31256 Distributor
DS31256 Circuit	DS31256 Reference	DS31256 PDF	DS31256 RoHS