DS31412

DS31412 Description

Maxim

6/8/12 Independent DS3/E3 Framers on a Single Die
Framing and Formatting to M23 DS3, C-Bit Parity DS3, and G.751 E3
LIU Interface can be Binary (NRZ) or Dual-Rail (POS/NEG)
B3ZS/HDB3 Encoder and Decoder
Generate and Detect DS3/E3 Alarms
Integrated HDLC Controller for Each Channel
Integrated FEAC Controller for Each Channel
Integrated Bit Error-Rate Tester (BERT) for Each Channel
Large Performance-Monitoring Counters
Line, Diagnostic, and Payload Loopbacks
Externally Controlled Transmit Overhead Insertion Port
Support External Timing or Loop-Timing
Framers can be Powered Down When Not Used
8-Bit Processor Port Supports Muxed or Nonmuxed Bus Operation (Intel or Motorola)
3.3V Supply with 5V Tolerant I/O
349-Pin, 27mm x 27mm BGA Package
IEEE 1149.1 JTAG Support

DS31412 Data Sheet	DS31412 Spec	DS31412 Application Notes	DS31412 Distributor
DS31412 Circuit	DS31412 Reference	DS31412 PDF	DS31412 RoHS