DSP56371

DSP56371 Description

DSP56371 Categories

DSP56371 Manufacturer

DSP56371 Datasheet (PDF)

DSP56371 Price & Availability

DSP56371 Features

• 1.25 V core with a 3.3 V peripheral I/O
• Object Code Compatible with the 56K core
• Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support
• Program Control with position independent code support and instruction cache support
• Six-channel DMA controller
• PLL based clocking with a wide range of frequency multiplications (1 to 255), predivider factors (1 to 3) and power saving clock divider (2^I: i=0 to 7). Reduces clock noise
• Internal address tracing support and OnCE^TM for Hardware/Software debugging
• JTAG port
• Very low-power CMOS design, fully static design with operating frequencies down to DC
• STOP and WAIT low-power standby modes
• EFCOP running concurrently with core