- Completely User-Code Compatible with the MC68040
- Superscalar Implementation of M68000 Architecture
- Branch Cache Reduces Branches to Zero Cycles
- Executes Three Instructions per Clock
- Dual 8K On-Chip Caches
- Bus Snooping
- Independent Instruction and Data Paged MMUs (MC68060 and MC68LC060 Only)
- Full 32-Bit Nonmultiplexed Address an Data Bus
- Power Management
- IEEE-Compatible On-Chip FPU (MC68060 Only)
- Available in 50 and 60 MHz Speeds (MC68060)
- Available in 50, 66 and 75 MHz Speeds (MC68LC060 and MC68EC060)
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