MC68360

MC68360 Manufacturer

MC68360 Description

MC68360 Categories

MC68360 Datasheet (PDF)

MC68360 Price & Availability

MC68360 Features

• CPU+ Processor (8.3 MIPS at 33MHz)
  • 32-bit version of the CPU32 core (fully compatible with CPU32)
• Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines
• Complete static design (0-33 MHz Operation)
• Slave mode to disable CPU32+ (allows use with external processors)
  • Multiple QUICCs can share one system bus (one master)
  • MC68040 companion mode allows QUICC to be an MC68040 companion chip and intelligent peripheral (29 MIPS at 33 MHz)
  • All QUICC features available in slave mode
• Memory controller (eight banks)
  • Contains complete Dynamic Random-Access Memory (DRAM) controller
  • Glueless interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access Memory (SRAM),
  • Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc.
  • Boot chip select available at Reset (options for 8-, 16-, or 32-bit memory)
  • Special features for MC68040 including Burst Mode
• Four general-purpose timers
  • Four 16-bit timers or two 32-bit timers
• Two Independent DMAs (IDMAs)
• System Integration Module (SIM60)

• Bus monitor
• Breakpoint logic provides on-chip H/W breakpoints
• Spurious interrupt monitor
• External masters may use on-chip features such as chip selects
• Periodic interrupt timer
• On-chip bus arbitration with no overhead for internal masters
• Low power stop mode
• IEEE 1149.1 Test Access Port

• RISC Communications Processor Module (CPM)
  • Many new commands (e.g., Graceful Stop Transmit, Close RxBD)
  • Supports continuos mode transmission and reception on all serial channels
  • 2.5 kbytes of dual-port RAM
  • 14 Serial DMA (SDMA) channels
  • Three parallel I/O registers with open-drain capability
  • Each serial channel can have its own Pins (NMSI mode)
• Four baud rate generators
• Four SCCs
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