54F280J-MLS
54F280J-MLS Description
9-Bit Parity Generator/Checker
54F280J-MLS Vendor
National Semiconductor
54F280J-MLS Features
  • Guaranteed 4000V minimum ESD protection
54F280J-MLS Description

    The 'F280 is a high-speed parity generator/checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH. If an even number of inputs is HIGH, the Sum Even output is HIGH. If an odd number is HIGH, the Sum Even output is LOW. The Sum Odd output is the complement of the Sum Even output.

54F280J-MLS Datasheet and Application Notes
ParameterValue
Temperature Min (deg C)-55
Temperature Max (deg C)125
PackageCERDIP
Pins14
StatusPreliminary
Pricing
Products related to 54F280J-MLS
54F280FMQB   54F280DMQB   JM38510/34901BDA   54F280LMQB   
54F280   JM38510/34901BCA   JM38510/34901B2A   

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