5962-8769701SSA

5962-8769701SSA Description

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5962-8769701SSA Datasheet (PDF)

5962-8769701SSA Price & Availability

5962-8769701SSA Features

• I_CC reduced by 50%
• Ideal for addressable register applications
• Clock enable for address and data synchronization applications
• Eight edge-triggered D flip-flops
• Buffered common clock
• Outputs source/sink 24 mA
• See '273 for master reset version
• See '373 for transparent latch version
• See '374 for TRI-STATE version
• 'ACT377 has TTL-compatible inputs
• Standard Microcircuit Drawing (SMD) -'AC377: 5962-88702 -'ACT377: 5962-87697

5962-8769701SSA Description

The 'AC/'ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

5962-8769701SSA Parameters

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