The 'ACT112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on S#_D or C#_D prevents clocking and forces Q or Q# HIGH, respectively. Simultaneous LOW signals on S#_D and C#_D force both Q and Q# HIGH.

Asynchronous Inputs:

LOW input to S#_D sets Q to HIGH level

LOW input to C#_D sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C#_D and S#_D makes both Q and Q#

HIGH