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5962-9091001MSA(54F377FMQB)

5962-9091001MSA(54F377FMQB) Description

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5962-9091001MSA(54F377FMQB) Manufacturer

5962-9091001MSA(54F377FMQB) Datasheet (PDF)

5962-9091001MSA(54F377FMQB) Price & Availability


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5962-9091001MSA(54F377FMQB) Features

  • Ideal for addressable register applications
  • Clock enable for address and data synchronization applications
  • Eight edge-triggered D flip-flops
  • Buffered common clock
  • See 'F273 for master reset version
  • See 'F373 for transparent latch version
  • See 'F374 for TRI-STATE® version
  • Guaranteed 4000V minimum ESD protection

5962-9091001MSA(54F377FMQB) Description

    The 'F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.

    The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

    5962-9091001MSA(54F377FMQB) Parameters

    StatusFull production
    PackageCERPACK
    Temperature Min (deg C)-55
    Temperature Max (deg C)125
    Pins20
    Pricing$10.20
    Select parameters and click to see components with these parameters.

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    Keywords
    5962-9091001MSA(54F377FMQB) Data Sheet 5962-9091001MSA(54F377FMQB) Spec 5962-9091001MSA(54F377FMQB) Application Notes 5962-9091001MSA(54F377FMQB) Distributor
    5962-9091001MSA(54F377FMQB) Circuit 5962-9091001MSA(54F377FMQB) Reference 5962-9091001MSA(54F377FMQB) PDF 5962-9091001MSA(54F377FMQB) RoHS