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DP83843

DP83843 Description

PHYTER

DP83843 Categories

Ethernet ICs

DP83843 Manufacturer

National Semiconductor

DP83843 Datasheet (PDF)

DP83843 Datasheet

DP83843 Price & Availability

Check DP83843 Price & Availability at Canics

DP83843 Features

IEEE 802.3 ENDEC with AUI/10BASE-T transceivers and built-in filters
IEEE 802.3u 100BASE-TX compatible - directly drives standard Category 5 UTP, no need for external 100BASE-TX transceiver
Fully Integrated and fully compliant ANSI X3.263 TP-PMD physical sublayer which includes adaptive equalization and BLW compensation
IEEE 802.3u 100BASE-FX compatible - connects directly to industry standard Electrical/Optical transceivers
IEEE 802.3u Auto-Negotiation for automatic speed selection
IEEE 802.3u compatible Media Independent Interface (MII) with Serial Management Interface
Integrated high performance 100 Mb/s clock recovery circuitry requiring no external filters
Full Duplex support for 10 and 100 Mb/s data rates
MII Serial 10 Mb/s mode
Fully configurable node/switch and 100Mb/s repeater modes
Programmable loopback modes for flexible system diagnostics
Flexible LED support
Single register access to complete PHY status
MDIO interrupt support
Individualized scrambler seed for 100BASE-TX applications using multiple PHYs
Low power consumption for multi-port applications
Small footprint 80-pin PQFP package

DP83843 Description

The DP83843BVJE is a full feature Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-X Ethernet protocols.

This VLSI device is designed for easy implementation of 10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media through an external transformer or to fiber media via industry standard electrical/optical fiber PMD transceivers.This device also interfaces directly to the MAC layer through the IEEE 802.3u standard Media Independent Interface (MII), ensuring interoperability between products from different vendors.

The DP83843 is designed with National Semiconductor?s advanced CMOS process. Its system architecture is based on the integration of several of National?s industry proven core technologies:

IEEE 802.3 ENDEC with AUI/10BASE-T transceiver module to provide the 10 Mb/s functions Clock Recovery/Generator Modules from National?s Fast Ethernet and FDDI products FDDI Stream Cipher scrambler/descrambler for TP-PMD 100BASE-X physical coding sub-layer (PCS) and control logic that integrate the core modules into a dual speed Ethernet physical layer controller ANSI X3T12 Compliant TP-PMD Transceiver technology with BLW compensation

DP83843 Parameters

Products Similar to DP83843

DP83843BVJE, DP83843BVJE/NOPB

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Keywords

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