JM38510/34102BFA
JM38510/34102BFA Description
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop
JM38510/34102BFA Vendor
National Semiconductor
JM38510/34102BFA Features
  • Guaranteed 4000V minimum ESD protection.
JM38510/34102BFA Description

    The 'F109 consists of two high-speed, completely independent transition clocked JK# flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK# design allows operation as a D flip-flop (refer to 'F74 data sheet) by connecting the J and K# inputs.

    Asynchronous Inputs:

    LOW input to S#D sets Q to HIGH level

    LOW input to C#D sets Q to LOW level

    Clear and Set are independent of clock

    Simultaneous LOW on C#D and S#D makes both Q and Q#

    HIGH

JM38510/34102BFA Datasheet and Application Notes
ParameterValue
Temperature Min (deg C)-55
Temperature Max (deg C)125
PackageCERPACK
Pins16
StatusFull production
Pricing$5.60
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