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TP3057MDC

TP3057MDC Manufacturer

TP3057MDC Description

TP3057MDC Datasheet (PDF)

TP3057MDC Datasheet

TP3057MDC Price & Availability


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TP3057MDC Features

  • Complete CODEC and filtering system (COMBO) including:
    • Transmit high-pass and low-pass filtering
    • Receive low-pass filter with sin x/x correction
    • Active RC noise filters
    • µ-law or A-law compatible COder and DECoder
    • Internal precision voltage reference
    • Serial I/O interface
    • Internal auto-zero circuitry
  • µ-law, 16-pin-TP3054
  • A-law, 16-pin-TP3057
  • Designed for D3/D4 and CCITT applications
  • ±5V operation
  • Low operating power-typically 50 mW
  • Power-down standby mode-typically 3 mW
  • Automatic power-down
  • TTL or CMOS compatible digital interfaces
  • Maximizes line interface card circuit density
  • Dual-In-Line or surface mount packages
  • See also AN-370, "Techniques for Designing with CODEC/Filter COMBO Circuits"

TP3057MDC Description

    The TP3054, TP3057 family consists of µ-law and A-law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in Figure 1, and a serial PCM interface. The devices are fabricated using National's advanced double-poly CMOS process (microCMOS).

    The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded µ-law or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded µ-law or A-law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats.

    TP3057MDC Parameters

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