ISP1161A

ISP1161A Description

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ISP1161A Manufacturer

ISP1161A Datasheet (PDF)

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ISP1161A Features

• Complies with Universal Serial Bus Specification Rev. 2.0
• The Host Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s); the Device Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s)
• Combines the HC and the DC in a single chip
• On-chip DC complies with most USB device class specifications
• Both the HC and the DC can be accessed by an external microprocessor via separate I/O port addresses
• Selectable one or two downstream ports for the HC and one upstream port for the DC
• High-speed parallel interface to most of the generic microprocessors and Reduced Instruction Set Computer (RISC) processors such as:
  • Hitachi ® SuperH^tmSH-3 and SH-4
  • MIPS-based^tmRISC
  • ARM7^tm, ARM9^tm, StrongARM ®
• Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC, 11.1 Mbyte/s data transfer rate between the microprocessor and the DC
• Supports single-cycle and burst mode DMA operations
• Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints for the DC
• Built-in separate FIFO buffer RAM for the HC (4 kbytes) and DC (2462 bytes)
• Endpoints with double buffering to increase throughput and ease real-time data transfer for both DC transfers and HC isochronous (ISO) transactions
• 6 MHz crystal oscillator with integrated PLL for low EMI
• Controllable LazyClock (100 kHz +-50pct) output during ?suspend?
• Clock output with programmable frequency (3 to 48 MHz)
• Software controlled connection to the USB bus (SoftConnect^tm) on upstream port for the DC
• Good USB connection indicator that blinks with traffic (GoodLink^tm) for the DC
• Software selectable internal 15 kOhm pull-down resistors for HC downstream ports
• Dedicated pins for suspend sensing output and wake-up control input