- Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. Vestigial Side Band (VSB) signals)
- Up to eight analog Y + C inputs, split as desired
- Up to four analog component inputs, with embedded or separate sync, split as desired
- Four on-chip anti-aliasing filters in front of the Analog-to-Digital Converters (ADCs)
- Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals
- Switchable white peak control
- Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz)
- Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties
- On-chip line-locked clock generation in accordance with "ITU 601"
- Requires only one crystal (32.11 or 24.576 MHz) for all standards
- Horizontal and vertical sync detection.
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