SCC68692

SCC68692 Manufacturer

SCC68692 Description

SCC68692 Categories

SCC68692 Datasheet (PDF)

SCC68692 Price & Availability

SCC68692 Features

• S68000 bus compatible
• Dual full-duplex asynchronous receiver/transmitters
• Quadruple buffered receiver data register
• Programmable data format:
  • 5 to 8 data bits plus parity
  • Odd, even, no parity or force parity
  • 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
• 16-bit programmable Counter/Timer
• Programmable baud rate for each receiver and transmitter selectable from:
  • 22 fixed rates: 50 to 115.2 k baud
  • Non-standard rates to 115.2 kb
  • Non-standard user-defined rate derived from programmable counter/timer
  • External 1X or 16X clock
• Parity, framing, and overrun error detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode
  • Normal (full-duplex)
  • Automatic echo
  • Local loopback
  • Remote loopback
  • Multidrop mode (also called ?wake-up? or ?9-bit?)
• Multi-function 6-bit input port
  • Can serve as clock or control inputs
  • Change of state detection on four inputs
  • Inputs have typically >100 k Ohm pull-up resistors
• Multi-function 8-bit output port
  • Individual bit set/reset capability
  • Outputs can be programmed to be status/interrupt signals
• Versatile interrupt system
  • Single interrupt output with eight maskable interrupting conditions
  • Interrupt vector output on interrupt acknowledge
  • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
• Maximum data transfer rates: 1X ? 1 MB/sec, 16X ? 125 kB/sec
• Automatic wake-up mode for multidrop applications
• Start-end break interrupt/status
• Detects break which originates in the middle of a character
• On-chip crystal oscillator
• Power down mode
• Receiver timeout mode
• Commercial and Industrial temperature r

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