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SCN2681T Features- Fast bus cycle times reduce or eliminate CPU wait states
- Dual full-duplex asynchronous receiver/transmitters
- Quadruple buffered receiver data registers
- Programmable data format
- 5 to 8 data bits plus parity
- Odd, even, no parity or force parity
- 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
- 16-bit programmable Counter/Timer
- Programmable baud rate for each receiver and transmitter selectable from:
- 22 fixed rates: 50 to 115.2 k baud
- Non-standard rates to 115.2
- Non-standard user-defined rate derived from programmable counter/timer
- External 1X or 16X clock
- Parity, framing, and overrun error detection
- False start bit detection
- Line break detection and generation
- Programmable channel mode
- Normal (full-duplex)
- Automatic echo
- Local loopback
- Remote loopback
- Multi-function programmable 16-bit counter/timer
- Multi-function 7-bit input port
- Can serve as clock or control inputs
- Change of state detection on four inputs
- 100 kOhm typical pull-up resistors
- Multi-function 8-bit output port
- Individual bit set/reset capability
- Outputs can be programmed to be status/interrupt signals
- Versatile interrupt system
- Single interrupt output with eight maskable interrupting conditions
- Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
- Maximum data transfer rates: 1X ? 1 MB/sec transmitter and receiver; 16X ? 500 kB/sec receiver and 250 kB/sec transmitter
- Automatic wake-up mode for multidrop applications
- Start-end break interrupt/status
- Detects break which originates in the middle of a character
- On-chip crystal oscillator
- Single +5 V power supply
- Commercial and industrial temperature range
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