TDA8762 Datasheet

10-bit resolution
Sampling rate up to 40 MHz
DC sampling allowed
One clock cycle conversion only
High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at f_clk= 40 MHz)
No missing codes guaranteed
In range (IR) TTL output
TTL compatible digital inputs and outputs
Low-level AC clock input signal allowed
External reference voltage regulator
Power dissipation only 380 mW (typical)
Low analog input capacitance, no buffer amplifier required
No sample-and-hold circuit required.

TDA8762