TDA8764 Datasheet

10-bit resolution (binary or gray code)
Sampling rate up to 40 MHz (/4 version)

Sampling rate up to 80 MHz (/8 version)
DC sampling allowed
One clock cycle conversion only
High signal-to-noise ratio over a large analog input frequency range (9.5 effective bits at 5 MHz; full-scale input at f_clk= 40 MHz)
No missing codes guaranteed
In-Range (IR) CMOS output
TTL and CMOS levels compatible digital inputs
2.7 to 3.6 V CMOS digital outputs
Low-level AC clock input signal allowed
Internal reference voltage regulator
Power dissipation only 250 mW (typical for /4 version)

Power dissipation only 375 mW (typical for /8 version)
Low analog input capacitance, no buffer amplifier required
No sample-and-hold circuit required.

TDA8764