S3C2800X

Samsung

Errata

Data Sheet

Errata

User's Manual

Application Note

Check S3C2800X Price & Availability at Canics

Architecture

ARM920T CPU core supports the Thumb instruction, ARM instruction, and core debug

Enhanced multiplier, JTAG, and the embedded ICE

Memory Management Unit (support virtual memory)

Internal AMBA bus architecture (AMBA 2.0, AHB/APB)

Maximum CPU clock frequency of 200MHz@1.8V



Memory Controller

Little-/Big-endian support for external memory.

Address space: 32Mbytes per each bank (Total 256Mbyte)

Supports programmable 8/16/32-bit data bus width for each memory bank

Fixed bank start address for all (static memory and dynamic memory banks)

8 memory banks

- 4 memory banks for static memory (ROM, SRAM, FLASH etc)

- 4 memory banks for dynamic memory (Fast Page, EDO, and Synchronous DRAM)

Fully programmable access cycles for all static memory banks

Supports external wait signal to extend the bus cycle

Supports self-refresh mode in DRAM/SDRAM.

Supports asymmetric/symmetric address of DRAM



I/D (Instruction/Data) Cache Memory

64-way set-associative ICache (16KB) and DCache (16KB)

8 words per line with one valid bit and 2 dirty bits per line

Pseudo-random or round-robin replacement algorithm

Write-through and Write-back cache operation.

The write buffer can hold 16 words of data and 4 addresses

Low voltage cache for reduced power consumption



Clock & Power Manager

The on-chip PLL generates the necessary clock for the operation of MCU at maximum of 200MHz@1.8V

Input frequency range: (Fin) = 6MHz - 10MHz.

Output frequency range: (FCLK) = 20MHz - 200MHz

Clock can be selectively provided to each function block by software

Power Down Mode: NORMAL, SLOW, and IDLE mode

- NORMAL mode: Normal operating mode

- SLOW mode: Low frequency clock without PLL

- IDLE mode: Clock to CPU is disabled



PCI Bus Interface

Embedded PC