74AC11008DR Datasheet

74AC11008DR Manufacturer

Texas Instruments

74AC11008DR Description

Quadruple 2-Input Positive-AND Gates

74AC11008DR Datasheet (PDF)

74AC11008DR Datasheet

74AC11008DR Features

Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)

74AC11008DR Parameters

Status	ACTIVE
Temp (oC)	-40 to 85
Budget Price ($US) \| QTY	1.10 \| 1KU
Package Type \| Pins	SOIC (D) \| 16
STD Pack QTY	2500
tpd max (ns)	6.9
Vcc range (V)	3.0 to 5.5
Voltage Nodes (V)	5, 3.3
Input Level	CMOS
Output Level	CMOS
No. of Gates	4
Static Current	0.04
Output Drive (mA)	-24/24

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