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74AC11245PWLE

74AC11245PWLE Description

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74AC11245PWLE Manufacturer

74AC11245PWLE Datasheet (PDF)

74AC11245PWLE Price & Availability


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74AC11245PWLE Features

  • 3-State Outputs Drive Bus Lines Directly
  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (NT)

74AC11245PWLE Parameters

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