74ALVTH16373ZQLR

74ALVTH16373ZQLR Description

State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus^TM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V V_CC)
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
High Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V V_CC)
Power Off Disables Outputs, Permitting Live Insertion
High-Impedance State During Power Up and Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
Auto3-State Eliminates Bus Current Loading When Output Exceeds V_CC + 0.5 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
Flow-Through Architecture Facilitates Printed Circuit Board Layout
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

74ALVTH16373ZQLR Data Sheet	74ALVTH16373ZQLR Spec	74ALVTH16373ZQLR Application Notes	74ALVTH16373ZQLR Distributor
74ALVTH16373ZQLR Circuit	74ALVTH16373ZQLR Reference	74ALVTH16373ZQLR PDF	74ALVTH16373ZQLR RoHS