CD4002BPW Manufacturer
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CD4002BPW Datasheet (PDF)
CD4002BPW Price & Availability
CD4002BPW Features- Propagation delay time = 60 ns (typ.) at CL= 50 pF, VDD= 10 V
- Buffered inputs and outputs
- Standardized symmetrical output characteristics
- 100% tested for maximum quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package temperature range):
1 V at VDD= 5 V
2 V at VDD= 10 V
2.5 V at VDD= 15 V - Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ?B? Series CMOS Devices"
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