CD40102BNSR DescriptionCD40102BNSR DescriptionCD40102BNSR DescriptionCD40102BNSR CategoriesCD40102BNSR Manufacturer
CD40102BNSR Datasheet (PDF)
CD40102BNSR Price & Availability
CD40102BNSR Features- Synchronous or asynchronous preset
- Medium-speed operation: fCL = 3.6 MHz (typ.) @ VDD = 10V
- Cascadable
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ?B? Series CMOS Devices"
- Applications:
- Divide-by-"N" counters
- Programmable timers
- Interrupt timers
- Cycle/program counter
CD40102BNSR Parameters
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Keywords
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