| CD40102BPW Description | | CMOS 8-Stage Presettable 2-Decade BCD Synchronous Down Counter | | CD40102BPW Vendor | | Texas Instruments | | CD40102BPW Features | - Synchronous or asynchronous preset
- Medium-speed operation: fCL = 3.6 MHz (typ.) @ VDD = 10V
- Cascadable
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Divide-by-"N" counters
- Programmable timers
- Interrupt timers
- Cycle/program counter
| | CD40102BPW Datasheet and Application Notes | | | Parameter | Value | | Voltage Nodes (V) | 5, 10, 15 | | Status | ACTIVE | | Temp (oC) | -55 to 125 | | Budget Price ($US) | QTY | 0.53 | 1KU | | Package Type | Pins | TSSOP (PW) | 16 | | STD Pack QTY | 90 | | Products related to CD40102BPW | CD40103BE CD40103BPW CD40103B CD40102BNSR
CD40103BNSR CD40102BPWR CD40102BE CD40103BF3A
CD40102B CD40103BPWR CD40103BF |
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