| CD40103BF Description | | CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter | | CD40103BF Vendor | | Texas Instruments | | CD40103BF Features | - Synchronous or asynchronous preset
- Medium-speed operation: fCL= 3.6 MHz (typ.) @ VDD= 10V
- Cascadable
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD= 5 V
2 V at VDD= 10 V
2.5 V at VDD= 15 V - Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Divide-by-"N" counters
- Programmable timers
- Interrupt timers
- Cycle/program counter
| | CD40103BF Datasheet and Application Notes | | | Parameter | Value | | Voltage Nodes (V) | 5, 10, 15 | | Vcc Range (V) | 3.0 to 18.0 | | Input Level | CMOS | | Output Level | CMOS | | Output Drive (mA) | -3.2/1 | | Status | ACTIVE | | Temp (oC) | -55 to 125 | | Budget Price ($US) | QTY | 3.09 | 1KU | | Package Type| Pins | CDIP (J) | 16 | | STD Pack QTY | 1 | | Products related to CD40103BF | CD40103BE CD40103BPW CD40103B CD40102BNSR
CD40103BNSR CD40102BPWR CD40102BE CD40103BF3A
CD40102B CD40102BPW CD40103BPWR |
|