CD4019BM96

CD4019BM96 Manufacturer

CD4019BM96 Description

CD4019BM96 Description

CD4019BM96 Datasheet (PDF)

CD4019BM96 Price & Availability

CD4019BM96 Features

• Medium speed operation??t_PHL= t_PLH= 60 ns (typ.) at C_L= 50 pF, V_DD= 10 V
• Standardized, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ?B? Series CMOS Devices"
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  
  1 V at V_DD= 5 V
  
  2 V at V_DD= 10 V
  
  2.5 V at V_DD= 15 V
• Applications:
  • AND-OR select gating
  • Shift-right/shift-left registers
  • True/complement selection
  • AND/OR/Exclusive-OR selection

CD4019BM96 Parameters

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