CD4021BF

CD4021BF Description

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CD4021BF Datasheet (PDF)

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CD4021BF Features

• Medium speed operation?12 MHz (typ.) clock rate at V_DD? V_SS= 10 V
• Fully static operation
• 8 master-slave flip-flops plus output buffering and control gating
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  
  1 V at V_DD= 5 V
  
  2 V at V_DD= 10 V
  
  2.5 V at V_DD= 15 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ?B? Series CMOS Devices"
• Applications:
  • Parallel input/serial output data queueing
  • Parallel to serial data conversion
  • General-purpose register

CD4021BF Parameters

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