CD4024BMT

CD4024BMT Description

CD4024BMT Description

CD4024BMT Description

CD4024BMT Categories

CD4024BMT Manufacturer

CD4024BMT Datasheet (PDF)

CD4024BMT Price & Availability

CD4024BMT Features

• Medium-speed operation
• Fully static operation
• Buffered inputs and outputs
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• Fully static operation
• Common reset
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range):
  
  1 V at V_DD= 5 V
  
  2 V at V_DD= 10 V
  
  2.5 V at V_DD= 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
• Applications:
  • Control counters
  • Timers
  • Frequency dividers
  • Time-delay circuits

CD4024BMT Parameters

Products Similar to CD4024BMT