| CD4027BPWR Description | | CMOS Dual J-K Master-Slave Flip-Flop | | CD4027BPWR Vendor | | Texas Instruments | | CD4027BPWR Features | - Set-Reset capability
- Static flip-flop operation — retains state indefinitely with clock level either "high" or "low"
- Medium speed operation — 16 MHz (typ.) clock toggle rate at 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD= 5 V
2 V at VDD= 10 V
2.5 V at VDD= 15 V - 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Registers, counters, control circuits
| | CD4027BPWR Datasheet and Application Notes | | | Parameter | Value | | Voltage Nodes (V) | 5, 10, 15 | | Status | ACTIVE | | Temp (oC) | -55 to 125 | | Budget Price ($US) | QTY | 0.24 | 1KU | | Package Type| Pins | TSSOP (PW) | 16 | | STD Pack QTY | 2000 | | Products related to CD4027BPWR | CD4027BNSR CD4027BM96 CD4027BF CD4027BF3A
JM38510/05152BEA CD4027BM CD4027BPW CD4027B
CD4027BMT CD4027BE |
|