| CD4029B Description | | CMOS Presettable Up/Down Counter | | CD4029B Vendor | | Texas Instruments | | CD4029B Categories | | | CD4029B Features | - Medium-speed operation… 8 MHz (typ.) @ CL= 50 pF and VDD–VSS= 10 V
- Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times
- "Preset Enable" and individual "Jam" inputs provided
- Binary or decade up/down counting
- BCD outputs in decade mode
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD= 5 V
2 V at VDD= 10 V
2.5 V at VDD= 15 V - Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Programmable binary and decade counting/frequency synthesizers-BCD output
- Analog to digital and digital to analog conversion
- Up/Down binary counting
- Magnitude and sign generation
- Up/Down decade counting
- Difference counting
| | CD4029B Datasheet and Application Notes | | | Parameter | Value | | Voltage Nodes (V) | 5, 10, 15 | | Vcc Range (V) | 3.0 to 18.0 | | Input Level | CMOS | | Output Level | CMOS | | Products related to CD4029B | CD4029BF3A CD4029BF CD4029BPWR CD4029BMT
CD4029BPW CD4029BE CD4029BM CD4029BNSR
CD4029BM96 8101602EA |
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