CD4029BPW

CD4029BPW Description

CD4029BPW Description

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CD4029BPW Manufacturer

CD4029BPW Datasheet (PDF)

CD4029BPW Price & Availability

CD4029BPW Features

• Medium-speed operation? 8 MHz (typ.) @ C_L= 50 pF and V_DD?V_SS= 10 V
• Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times
• "Preset Enable" and individual "Jam" inputs provided
• Binary or decade up/down counting
• BCD outputs in decade mode
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  
  1 V at V_DD= 5 V
  
  2 V at V_DD= 10 V
  
  2.5 V at V_DD= 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ?B? Series CMOS Devices"
• Applications:
  • Programmable binary and decade counting/frequency synthesizers-BCD output
  • Analog to digital and digital to analog conversion
  • Up/Down binary counting
  • Magnitude and sign generation
  • Up/Down decade counting
  • Difference counting

CD4029BPW Parameters

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