CD4030BMT

CD4030BMT Manufacturer

CD4030BMT Description

CD4030BMT Description

CD4030BMT Datasheet (PDF)

CD4030BMT Price & Availability

CD4030BMT Features

• Medium-speed operation?t_PHL, t_PLH= 65 ns (typ.) at V_DD= 10 V, C_L= 50 pF
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range) =
  
  1 V at V_DD= 5 V
  
  2 V at V_DD= 10 V
  
  2.5 V at V_DD= 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ?B? Series CMOS Devices"
• Applications:
  • Even and odd-parity generators and checkers
  • Logical comparators
  • Adders/subtractors
  • General logic functions

CD4030BMT Parameters

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