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CD4031BPW Datasheet (PDF)
CD4031BPW Price & Availability
CD4031BPW Features- Fully static operation: DC to 12 MHz typ. @ VDD- VSS= 15 V
- Standard TTL drive capability on Q output
- Recirculation capability
- Three cascading modes:
- Direct clocking for high-speed operation
- Delayed clocking for reduced clock drive requirements
- Additional 1/2 stage for slow clocks
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°C
- Noise margin (over full package-temperature range):
1 V at VDD= 5 V
2 V at VDD= 10 V
2.5 V at VDD= 15 V - 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- Serial shift register
- Time delay circuits
CD4031BPW Parameters
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