4-Stage clocked shift operation
Synchronous parallel entry on all 4 stages
JK\ inputs on first stage
Asynchronous True/Complement control on all outputs
Static flip-flop operation; Master-slave configuration
Buffered inputs and outputs
High speed ? 12 MHz (typ.) at V_DD= 10 V
100% tested for quiescent current at 20 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
Applications:
- Counters, Registers
  - Arithmetic-unit registers
  - Shift-left ? shift right registers
  - Serial-to-parallel/parallel-to-serial conversions
- Sequence generation
- Control circuits
- Code conversion

CD4035BM96 Parameters

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