| CD4042BF Description | | CMOS Quad Clocked 'D' Latch | | CD4042BF Vendor | | Texas Instruments | | CD4042BF Features | - Clock polarity control
- Q and Q\ outputs
- Common Clock
- Low power TTL compatible
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- 5-V, 10-V, and 15-V parametric ratings
- Noise margin (full package-temperature range) =
1 V at VDD= 5 V
2 V at VDD= 10 V
2.5 V at VDD= 15 V - Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Buffer storage
- Holding register
- General digital logic
| | CD4042BF Datasheet and Application Notes | | | Parameter | Value | | Voltage Nodes (V) | 5, 10, 15 | | Status | ACTIVE | | Temp (oC) | -55 to 125 | | Budget Price ($US) | QTY | 2.37 | 1KU | | Package Type| Pins | CDIP (J) | 16 | | STD Pack QTY | 1 | | Products related to CD4042BF | CD4042BPWR CD4042BDWR CD4042BM CD4042BPW
CD4042BDW CD4042BNSR CD4042BD CD4042BDR
CD4042B CD4042BE CD4042BF3A CD4042BDT
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