| CD4043BPW Description | | CMOS Quad NOR R/S Latch with 3-State Outputs | | CD4043BPW Vendor | | Texas Instruments | | CD4043BPW Features | - 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package temperature range):
- 1 V at VDD= 5 V
- 2 V at VDD= 10 V
- 2.5 V at VDD= 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4043B for positive logic systems
- CD4044B for negative logic systems
| | CD4043BPW Datasheet and Application Notes | | | Parameter | Value | | Voltage Nodes (V) | 5, 10, 15 | | Status | ACTIVE | | Temp (oC) | -55 to 125 | | Budget Price ($US) | QTY | 0.24 | 1KU | | Package Type| Pins | TSSOP (PW) | 16 | | STD Pack QTY | 90 | | Products related to CD4043BPW | CD4044BM CD4043BDR CD4044BF CD4044B
CD4044BDWR CD4044BDT CD4044BE CD4043BD
CD4043BPWR CD4043BM CD4044BDR CD4044BPWR
CD4043BDWR CD4044BF3A CD4044BD CD4044BDW
CD4043BDW CD4043BNSR CD4043BDT CD4043BF3A
CD4043B CD4044BNSR CD4043BE CD4044BPW
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